1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device and particularly, but not limited to, a method of forming a barrier metal and a metal buried in a depression formed in a substrate. The present application is based on Japanese Patent Application No. 2001-148585, which is incorporated herein by reference.
2. Description of the Related Art
Conventional semiconductor integrated circuits have been using, as a material for metal wiring, aluminum or an aluminum-based metal composed of an aluminum alloy because these materials exhibit lower specific resistance and permit easier patterning. Recently, however, a Cu or Cu-based metal composed of a Cu alloy is being used that exhibits lower resistivity and higher electromigration (EM) resistance than those of aluminum-based metals. This trend is based on the recent increasing demand for higher integration, more compactness, higher speed, and higher reliability in semiconductor integrated circuit, such as LSIs.
To make wires by using such a Cu-based metal, it is difficult to form a desired wire because the Cu-based metal does not permit easy dry etching. A method has been disclosed in Japanese Patent Application Laid-Open No. 2000-183160, wherein a concave (trench) of a wiring pattern is formed in an interlayer dielectric, a Cu film is deposited on the entire surface, the trench is embedded, and chemical mechanical polishing (CMP) is carried out to remove the Cu film exposed on the interlayer dielectric so as to form an embedded wiring with the Cu film left in the trench. This technique is known as a damascene process. The damascene process may be divided into a single damascene process whereby only wiring is formed and a dual damascene process whereby contact holes or via holes for the connection with the wiring of a lower layer are also formed in addition to wiring. The dual damascene structure permits the number of steps to be reduced, thus contributing to reduced cost. As the method for filling a wire or the recessed portion between a wire and a via hole with a Cu film, the high-temperature reflow method, the sputtering method, and the electrolytic plating method are known, among which the electrolytic plating method is ideally used for filling a recessed portion exhibiting a high aspect ratio.
FIGS. 1A through 1E illustrate the dual damascene process. Referring to FIG. 1A, a first metal wire 103 having a barrier metal layer 102 and an interlayer dielectric 104 covering the first metal wire 103 are formed on a semiconductor substrate 101 on which elements have been formed. Then, a wiring trench 105 and a via hole 106 connected to the first metal wire 103 through the trench 105 are opened in the surface of the interlayer dielectric 104 by lithography and dry etching. Subsequently, as shown in FIG. 1B and FIG. 1C, a barrier metal layer 107 made of Ta or the like and a seed layer 108 made of Cu or the like are formed in sequence onto the inner surfaces of the trench 105 and the via hole 106 by a barrier metal/seed layer forming apparatus. The barrier metal layer and the seed layer are processed in the same vacuum atmosphere. Thereafter, as shown in FIG. 1D, the recessed portion of the via hole 106 and the trench 105 is filled with a plating metal 109 by plating method or the like wherein the seed layer 108 provides a plating electrode. The plating metal 109 is formed integrally with the seed layer 108. Next, as shown in FIG. 1E, the plating metal 109, the seed layer 108, and the barrier metal layer 107 that expose on the interlayer dielectric 104 are polished to be removed by the CMP method so as to form a second wire 110 and a contact hole 111 filled with the metal. Repeating the above procedure forms multilayer wiring.
To fill the recessed portion of the trench and via hole or the like with a metal film formed of Cu or the like by the electrolytic plating method, it is necessary to form a seed Cu layer providing a cathode in the plating process on the side surfaces and the bottom surface of the recessed portion in advance. By using the sputtering method, the barrier metal layer, which provides a Cu barrier layer, and the seed Cu layer are formed on the interlayer dielectric including the recessed portion, then plating is carried out to fill the recessed portion with Cu, using the seed layer as the cathode.
There has been accelerating demand for smaller wiring widths with the increasing microminiaturization of semiconductor integrated circuits. With this trend, the aspect ratios of trench and via holes are increasing. Via holes having an aspect ratio exceeding 4, for example, require filling by Cu. However, in the case of the trench and via hole or the like having high aspect ratios, as shown in the photograph of FIG. 8 and FIG. 11 showing the schematic diagrams of the photograph of FIG. 8, when an attempt is made to form the seed Cu layer 108 by sputtering on the bottom surface and side surfaces thereof after forming the barrier metal layer 107 on the inner surface of the recessed portion 106, there are some cases where adequate coverage is not accomplished.
Especially on the side surfaces near the bottom of the recessed portion 106, the seed Cu layer 108 is attached in a minute island state rather than being a continuous layer. For this reason, in this area, Cu hardly or insufficiently grows from the seed Cu layer 108 even when the plating is carried out. This happens because a Cu electrolytic plating bath (CuSO4.5H2O+H2SO4) exhibits strong acidity, so that the island-like seed Cu layer is melted away by the electrolytic plating bath faster than the growth of the Cu layer by the plating. Thus, the Cu is grown by the plating in the upper area of the recessed portion 106, that is, the area where the seed Cu layer 108 has been continuously formed, while Cu hardly or insufficiently grows in the lower area of the recessed portion 106, that is, the area where the seed Cu layer 108 has been formed in the island state. As a result, the recessed portion 106 cannot be completely filled with Cu, leading to the formation of voids.
To improve the poor formation the seed layer on the lower area of the recessed portion, it can be considered to increase the thickness of the seed layer by, for example, extending the sputtering time. In this case, however, the seed layer would be thick at the opening of the recessed portion, causing the seed layer to considerably overhang. As a result, the Cu that has grown at the opening before the filling of the recessed portion is completed may close or pinch off the opening, causing a large void to be formed in the recessed portion. Therefore, the thickness of the seed layer cannot be increased much.
As a solution to the above problem, Japanese Unexamined Patent Publication No. 2000-183160 has disclosed a method in which the seed layer formed by electroless plating is reinforced to prevent the seed layer from being formed in an island state, then electrolytic plating is carried out to charge Cu. According to this method, however, a plating apparatus is required to be additionally equipped with a plating bath for performing the electroless plating, posing a problem of a more complicated apparatus. This is another problem in that the electroless plating is generally poor in the aspect of stability and reproducibility, leading to poor mass productivity.
To improve the coverage of a seed layer, it is conceivable to use a long slow sputtering method in which the distance between a substrate and a target is set to be longer than usual or an ionized sputtering method in which Cu is ionized and Cu ions are positively drawn into a recessed portion by applying a substrate bias. However, even if these methods are used, because the side walls of the recessed portion have a relatively thinner seed Cu layer, the temperature of the substrate increases due to the bombardment of sputtered atoms, ions, etc. during a sputtering process, leading to a problem in that the seed Cu layer agglomerates. More specifically, the seed Cu layer formed on a barrier metal layer tends to minimize the energy of the Cu layer itself; therefore, if it is subjected to a temperature or other type of energy that is sufficient to provide the surface migration of Cu atoms, then it agglomerates. The agglomeration that takes place when the seed Cu layer is formed with the temperature of the holder for forming the seed Cu layer being set at 80xc2x0 C. is shown by the photograph of FIG. 9A and FIG. 12A, which is a schematic diagram of the photograph of FIG. 9A. When the temperature during the layer formation is high, the seed Cu layer 108 agglomerates in the island state. If Cu plating is carried out using the seed Cu layer that has agglomerated as mentioned above, the embedding failure of Cu 109 occurs, as shown in the photograph of FIG. 9B and FIG. 12B, which is a schematic diagram of the photograph of FIG. 9B. More specifically, when plating is carried out to fill the trench with a plating metal, the seed Cu layer on the substrate provides the cathode for the plating. No or insufficient Cu precipitation takes place in an area not covered by the seed Cu layer, resulting in filling failure. Hence, an embodiment in accordance with the present invention takes a manufacturing method described below.
A first aspect of the method of manufacturing semiconductor device according to the present invention comprises cooling a semiconductor substrate for such a time which prevents a seed layer from cohering before transferring the semiconductor substrate into a seed layer forming chamber at a predetermined temperature in a barrier metal layer and a seed layer forming process. In a second aspect of the present invention, the predetermined temperature is preferably 40 centigrade below zero. In a third aspect of the present invention, cooling the semiconductor substrate is preferably performed in a barrier metal forming chamber in a vacuum. In a fourth aspect of the present invention, cooling the semiconductor substrate is preferably performed in a chamber other than the seed layer forming chamber or the barrier metal forming chamber.
In order to restrain the agglomeration of the seed layer caused by a rise in temperature, the temperature during the formation of the seed layer, e.g., the temperature of the wafer holder for retaining a wafer, is lowered as much as possible, to cool a semiconductor substrate to preferably xe2x88x9240xc2x0 C. However, a agglomeration-free, smooth seed layer cannot be produced simply by maintaining a low temperature during the formation of the seed layer. This is because a temperature rise in a substrate while the barrier metal layer is being formed before the seed layer is formed is considered to affect the formation of the seed layer. For example, the time for cooling a wafer before forming the seed layer is set to 60 seconds, and the time for forming the seed layer is set to 60 seconds, so that the total treatment time in the chamber for forming the seed layer is 120 seconds (the 60-second cooling time plus the 60-second layer forming time). The total time for forming the barrier metal layer is set to 50 seconds. The treatment can be accomplished by using one chamber for forming a barrier metal layer and another chamber for forming a seed layer, as shown in the timing chart of FIG. 2A, which is referred to as xe2x80x9csingle modexe2x80x9d. In this case, the time for forming the seed layer is longer than the time for forming the barrier metal layer. Therefore, while a wafer is under the treatment, the next wafer waits for about 70 seconds in the chamber for forming the barrier metal layer, then the wafer is carried into the chamber for forming the seed layer to cool the wafer and deposit the layer thereon. It has been verified that this case permits the restraint of the agglomeration of the seed layer. In FIG. 2A, the thick lines indicate the processing time, while the thin lines indicate the waiting time.
As shown in FIG. 3A, it has been verified that the agglomeration of the seed layer can be restrained by setting the waiting time in the barrier metal layer forming chamber after the barrier metal layer has been formed to 50 seconds or more, as a result of a test performed by the invention.
The seed layer may be formed using seed layer forming chambers A and B in parallel, which is the comparative example, as shown in the timing chart of FIG. 2B. This case is referred to as xe2x80x9cdual modexe2x80x9d. In the dual mode, the time for which a wafer waits in the barrier metal layer forming chamber after the barrier metal layer has been deposited is reduced to 10 seconds or less, permitting higher processing efficiency to be achieved. However, despite the 60-second cooling in the seed layer forming chamber, the seed layer has developed agglomeration. In FIG. 2B, the thick lines indicate the processing time, while the thin lines indicate the waiting time. In this case, the agglomeration of the seed layer cannot be restrained even by extending the cooling time in the seed layer forming chamber to 120 seconds, as shown in FIG. 3B.
The single mode and the dual mode require the same time for the transfer from the barrier metal layer forming chamber to the seed layer forming chamber. The waiting time of a wafer in the barrier metal layer forming chamber is 70 seconds in the single mode, while it is 10 seconds in the dual mode. The difference in the waiting time significantly influences the agglomeration of the seed layer. As shown in FIG. 3A, the agglomeration problem of the seed layer can be solved by retaining a wafer in the barrier metal layer forming chamber for 50 seconds or more to cool the wafer after completing the deposition of the barrier metal layer, then carrying the wafer into the seed layer forming chamber to deposit the seed layer.